IJSTR

International Journal of Scientific & Technology Research

IJSTR@Facebook IJSTR@Twitter IJSTR@Linkedin
Home About Us Scope Editorial Board Blog/Latest News Contact Us
CALL FOR PAPERS
AUTHORS
DOWNLOADS
CONTACT
QR CODE
IJSTR-QR Code

IJSTR >> Volume 1 - Issue 2, March 2012 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



A new Method for Optimizing Energy Efficiency of Embedded Systems

[Full Text]

 

AUTHOR(S)

Akbar Bemana

 

KEYWORDS

Embedded Systems; Cache Memory; Leakage Power; Dynamic Energy; Nanometer Technology.

 

ABSTRACT

Several studies have shown that about 40% or more of the energy consumption on embedded systems that are based on microprocessor relates to cache. In technology with micrometer scaling, dynamic power was the primary contributor to total power dissipation of a CMOS design, but in technology with nanometer scaling, the share of leakage power in total Power consumption of energy continues to grow. In this paper we concentrate on the selection of optimal cache size for low energy consumption embedded systems. Our study is based on three different technologies on embedded systems. Results show that cache size should change for minimizing energy consumption in different technologies due to the increase of leakage power and decrease of dynamic energy as technology is shrinking. Our studies reveal that cache size changes depend on the rate at which cache miss increases when reducing the cache size. Our experiments show that through technology-aware cache configuration selection, we can reduce the energy consumption by 54% in average and maximum 75%.

 

REFERENCES

[1] D. Tarjan, Sh. Thoziyoor, N. P. Jouppi, Cacti 5.0, HP Laboratories, Technical Report, 2007.
[2] C. Zhang, F. Vahid, and W. Najjar, A Highly Configurable Cache Architecture for Embedded Systems, ACM Transactions on Embedded Computing Systems, Vol. 4, No. 2, May 2005.
[3] V.G. Moshnyaga, K. Inoue, Low-Power Cache Design, in Low-Power Electronics Design, C. Piguet Eds.,CRC Press, 2005.
[4] D. H. Albonesi, Selective cache ways: On-demand cache resource allocation, 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999.
[5] C. Zhang, F. Vahid and R. Lysecky, A self-Tuning Cache Architecture for Embedded Systems, in Proc. of DATE, 2004.
[6] Y. Cai, M. T. Schmitz, A. Ejlali, B. M. Al-Hashimi, and S. M. Reddy, Cache Size Selection for Performance, Energy and Reliability of Time-Constrained Systems, ASP-DAC 2006.
[7] K. Inoue, T. Ishihara, and K. Murakami, Waypredictive set-associative cache for high performance and low energy consumption, International Symposium on Low Power Electronic Design, 1999.
[8] H. Noori, M. Goudarzi, K. Inoue, and K. Murakami, "The Effect of Nanometer-Scale Technologies on the Cache Size Selection for Low Energy Embedded Systems," International Conference on Embedded Systems & Applications, 2007.
[9] SimpleScalar, www.simplescalar.com
[10] Mibench, www.eecs.umich.edu/mibench/