Redundant Radix4 Arithmetic Coprocessor Design Using VHDL
[Full Text]
AUTHOR(S)
Ashish Manoharrao Ingale, Ameed Mustafa Shah
KEYWORDS
VLSI, RR4, FPGA, MULTIPLIER, COPROCESSOR
ABSTRACT
With the growth of VLSI processing in the industrial sector the design of efficient algorithms for designing compact functional circuits has led to a competition among various industries. Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Some are more suitable for FPGA use than others. In the area of designing fast parallel algorithms for multiplying numbers, proposed algorithm for multiplying two nbit signed binary numbers needs é 2.71 log2 nù + 3 steps of single bit addition on an n ´n systolic architecture which outperforms the then best VLSI implementable algorithm with O(n) time and O(n2 ) hardware. The subsequent algorithms proposed by him for multiplying numbers in ternary and redundantradixfour (RR4) representations require still less time with 2 élog2n ù + 2 and é(1/2) log2n +1ù steps of single digit addition, respectively. Here we have proposed a novel approach for the multiplication of two numbers in RR4 number system. The results has been evaluated in ISE environment and the performance giving satisfactory results.
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