IJSTR

International Journal of Scientific & Technology Research

IJSTR@Facebook IJSTR@Twitter IJSTR@Linkedin
Home About Us Scope Editorial Board Blog/Latest News Contact Us
CALL FOR PAPERS
AUTHORS
DOWNLOADS
CONTACT
QR CODE
IJSTR-QR Code

IJSTR >> Volume 5 - Issue 4, April 2016 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Redundant Radix-4 Arithmetic Coprocessor Design Using VHDL

[Full Text]

 

AUTHOR(S)

Ashish Manoharrao Ingale, Ameed Mustafa Shah

 

KEYWORDS

VLSI, RR4, FPGA, MULTIPLIER, COPROCESSOR

 

ABSTRACT

With the growth of VLSI processing in the industrial sector the design of efficient algorithms for designing compact functional circuits has led to a competition among various industries. Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Some are more suitable for FPGA use than others. In the area of designing fast parallel algorithms for multiplying numbers, proposed algorithm for multiplying two n-bit signed binary numbers needs é 2.71 log2 nù + 3 steps of single bit addition on an n ´n systolic architecture which outperforms the then best VLSI implementable algorithm with O(n) time and O(n2 ) hardware. The subsequent algorithms proposed by him for multiplying numbers in ternary and redundant-radix-four (RR-4) representations require still less time with 2 élog2n ù + 2 and é(1/2) log2n +1ù steps of single digit addition, respectively. Here we have proposed a novel approach for the multiplication of two numbers in RR4 number system. The results has been evaluated in ISE environment and the performance giving satisfactory results.

 

REFERENCES

[1] Sriharish, L., & Kamaraju, M. (2014). A Novel VLSI Architecture of Multiplier on Radix 4 using Redundant Binary Technique. International Journal of Computer Applications, 103(2), 23-28.

[2] Antelo, E., Villalba, J., Bruguera, J. D., & Zapata, E. L. (1997). High performance rotation architectures based on the radix-4 CORDIC algorithm. Computers, IEEE Transactions on, 46(8), 855-870.

[3] Li, C. C., & Chen, S. G. (1997, April). A radix-4 redundant CORDIC algorithm with fast on-line variable scale factor compensation. In Acoustics, Speech, and Signal Processing, 1997. ICASSP-97., 1997 IEEE International Conference on (Vol. 1, pp. 639-642). IEEE.

[4] Seo, Y. H., & Kim, D. W. (2010). A new VLSI architecture of parallel multiplier–accumulator based on Radix-2 modified Booth algorithm. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on, 18(2), 201-208.

[5] He, Y., Chang, C. H., Gu, J., & Fahmy, A. H. (2005, May). A novel covalent redundant binary Booth encoder. In Circuits and Systems, 2005. ISCAS 2005. IEEE International Symposium on (pp. 69-72). IEEE.

[6] Wu, H., Hasan, M. A., Blake, I. F., & Gao, S. (2002). Finite field multiplier using redundant representation. Computers, IEEE Transactions on, 51(11), 1306-1316.

[7] M. De and B. P. Sinha, “Fast Parallel multiplication using redundant quarternary number system”, Parallel Processing Letters, Vol. 7, pp. 13-23 1997.

[8] Alodeep Sanyal, Rajat Shuvra Ghoshal, Achintya Das and Susmita Sur-Kolay A Reconfigurable Coprocessor for Redundant Radix-4 Arithmetic.

[9] M. De and B. P. Sinha, “Fast Parallel multiplication using redundant quarternary number system”, Parallel Processing Letters, Vol. 7, pp. 13-23 1997.

[10] S. Nakamura, “Algorithms for iterative array multiplication”, IEEE Trans. Comput., Vol.35, pp.713- 719, 1986.

[11] N. Takagi, H. Yassura, S Yajima, “High Speed VLSI multiplication algorithm with a redundnt binary addition tree” IEEE Trans. Comput., Vol. 34, pp. 789-796, 1985.

[12] B. P. Sinha and P. K. Srimani, “Fast parallel algorithms for binary multiplication and their implementation on systolic architectures”, IEEE Trans. Comput., Vol. 38, pp. 424- 431, 1989.

[13] M. De and B. P. Sinha, “Fast parallel algorithm for ternary multiplication using multivalued I2 L technology”, IEEE Trans. Comput., Vol. 43, pp. 603-607, 1994. R. P. Brent and H.T. Kung, “A regular layout for parallel adders”, IEEE Trans.

[14] Comput., Vol. 31, pp. 260-264,1982.

[15] K. Mehlhorn and F. P. Preparata, “Area-time optimal VLSI integer multiplier with minimum computation time”, Information and Control, Vol. 58, pp. 137-156, 1983.

[16] Karatsuba and Y. Ofman, “Multiplication of multi- digit numbers on automata,” Soviet Physics Doclady, Vol. 7, pp-595-596, 1963.

[17] N. Takagi and S. Yajima, “Modular multiplication hardware algorithms with a redundant representation and their application to RSA cryptosystem,” IEEE Trans. Comput., Vol. 41, pp. 887-891, 1992.

[18] Avizienis, “Signed-digit number representation for fast parallel arithmetic,” IRE Trans. Electron. Comput., Vol. EC-10, pp. 389-400, 1961.

[19] P. J. Ashenden, The designer’s guide to VHDL. San Francisco, California: Morgan Kaufman Publishers Inc. 1996.

[20] V. Vetz, J. Rose, A Marquardt, Architecture and CAD for deep-submicron FPGAs. USA: Kluwer Academic Publishers, 1999.

[21] Z. Salcic, VHDL and FPLDs in digital systems design, prototyping and customisation. USA: Kluwer Academic Publishers, 1998.

[22] Xilinx Data Book, 2000.