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IJSTR >> Volume 2- Issue 5, May 2013 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Implementation Of Network On-Chip Using GALS Scheme

[Full Text]

 

AUTHOR(S)

B. Nagaveni, G. Sai Thirumal, M. Rami Reddy

 

KEYWORDS

Index Terms: CDMA (Code Division Multiple Access), IC (Integrated Circuit Design), NoC (Network on-Chip), GALS (Globally Asynchronous Locally Synchronous), RTL (Register Transfer Level), VHDL (VHSIC Hardware Descriptive Language), FPGA (Field Programmable Gate Array).

 

ABSTRACT

Abstract: The Network-on-Chip (NOC) concept has recently become a widely discussed technique for handling the large on-chip communication requirements of complex System-on- Chip (SOC) designs. A traditional bus-based interconnection scheme does not scale well to very large SOCs because many Intellectual Property (IP) blocks must contend with each other to communicate over the shared bus. In contrast, an on-chip network uses the packet-switching paradigm to route information between IP blocks and it can be scaled up to achieve a very large total aggregate bandwidth within the chip. The issues of applying the Code-Division Multiple Access (CDMA) technique to an on-chip packet switched communication network are discussed in this paper. A packet switched Network-on-Chip (NOC) that applies the CDMA technique is realized in Register-Transfer Level (RTL) using VHDL. The realized CDMA NOC supports the Globally-Asynchronous Locally-Synchronous (GALS) communication scheme by applying both synchronous and asynchronous designs. In a packet switched NOC, which applies a point-to-point connection scheme, e.g., a ring topology NOC, data transfer latency varies largely if the packets are transferred to different destinations or to the same destination through different routes in the network. The CDMA NOC can eliminate the data transfer latency variations by sharing the data communication media among multiple users concurrently. A six-node GALS CDMA on-chip network is modeled and simulated. The characteristics of the CDMA NOC are examined by comparing them with the characteristics of an on-chip bidirectional ring topology network. The simulation results reveal that the data transfer latency in the CDMA NOC is a constant value for a certain length of packet and is equivalent to the best case data transfer latency in the bidirectional ring network when data path width is set to 32 bits.

 

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