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IJSTR >> Volume 1 - Issue 5, June 2012 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Design And Analysis of Clocked Subsystem Elements Using Leakage Reduction Technique

[Full Text]

 

AUTHOR(S)

Sanjay Singh, S.K. Singh, Mahesh Kumar Singh, Raj Kumar Sagar

 

KEYWORDS

Flip-flop, leakage power, stack transistor and pulse generator.

 

ABSTRACT

As the density and operating speed of CMOS VLSI chips increases, leakage power dissipation becomes more and more significant. This paper presents a leakage power behavior in Pulse triggered flip-flop. All the designs are simulated with and without the application of leakage reduction techniques and the readings are presented. By analyzing the leakage path of flip flops we propose a method to reduce the leakage power of flip flops in this paper. The circuit are simulated using TANNER Tool SPICE simulator. The result at a frequency of 400MHz shows that proposed Flip-flop consume less power.

 

REFERENCES

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