IJSTR

International Journal of Scientific & Technology Research

IJSTR@Facebook IJSTR@Twitter IJSTR@Linkedin
Home About Us Scope Editorial Board Blog/Latest News Contact Us
CALL FOR PAPERS
AUTHORS
DOWNLOADS
CONTACT
QR CODE
IJSTR-QR Code

IJSTR >> Volume 1 - Issue 5, June 2012 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Design And Analysis of Logic Gates Using Static And Domino Logic Technique

[Full Text]

 

AUTHOR(S)

Permendra Kr. Verma, S. K. Singh, Amit Kumar, Sanjay Singh

 

KEYWORDS

Static CMOS, Dynamic CMOS, PMOS, NMOS, Power-Saving Clock, Power-Wasting Glitches, Precharge, Logic Gate.

 

ABSTRACT

This paper presents a new design of static and Domino logic using CMOS. Domino logic is a CMOS based evolution of the dynamic logic techniques based on either PMOS or NMOS transistors. It allows a rail-to-rail logic swing. It was developed to speed up circuits in Dynamic Logic. They have smaller areas than conventional CMOS logic (as does all Dynamic Logic) and parasitic capacitances are smaller so that higher operating speeds are possible. There are many solutions to the problem of how to cascade dynamic logic gates. One way is Domino Logic, which inserts an ordinary static inverter between stages. While this might seem to defeat the point of dynamic logic, since the inverter has a PFET (one of the main goals of Dynamic Logic is to avoid PFETs where possible, due to speed), there are two reasons it works well.

 

REFERENCES

[ 1]. Madhuban Kishor et. al.,“Threshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families,” IEEE, 2000.
[ 2]. Massimo Alioto et. al., “Design of High-Speed Power-Efficient MOS Current-Mode Logic Frequency Dividers”, IEEE Transactions On Circuits And Systems—Ii: Express Briefs, Vol. 53, No. 11, November 2006.
[ 3]. R. H. Krambeck, C. M. Lee, and H. S. Law, “High-Speed Compact Circuits with CMOS”, in IEEE Journal of Solid State Circuits, pp 614-619, Vol. SC-17, No. 3, June 1982.
[ 4]. N. F. Goncalves and H. J. De Man, “NORA: A Race free Dynamic CMOS Technique for Pipelined Logic Structures”, in IEEE Journal of Solid State Circuits, pp 261-266, Vol. 18, No. 3, June 1983.
[ 5]. M. R. Prasad, D. Kirkpatrick, and R. K. Brayton, “Domino Logic Synthesis and Technology Mapping”, in International Workshop on Logic Synthesis, 1987.
[ 6]. Min Zhao and Sachin S. Sapatnekar, “Technology Mapping for Domino Logic”, in IEEE/ACM Proc. of Design Automation Conference, pp 248-251, 1998.
[ 7]. R. K. Brayton, R. L. Rudell, and A. L. Sangiovanni-Vincentelli, “MIS: A Multiple-Level Logic Optimization System”, in IEEE Trans. on Computer Aided Design, pp. 1062-1081, Vol. 6, No. 6, 1987.
[ 8]. Tyler Thorp, Gin Yee and Carl Sechen, “Domino Logic Synthesis Using Complex Static Gates”, in Proc. of Int’l Conference on Computer Aided Design, pp 242-247, 1998.
[ 9]. Abul Sarwar, “CMOS Power Consumption and Cpd Calculation”, Texas Instruments Incorporated, June 1997.

[ 10]. Ge Yang et. al, “Low Power and High Performance Circuit Techniques for High Fan-in Dynamic Gates”, IEEE Computer Society, 2004.

[ 11]. Douglas A. Pucknell and Kamran Eshraghian, “Basic VLSI Design” 3rd Edition 2011.

[ 12]. Wai Lee, Uming KO, P.T. Balsara, "A comparative Study on CMOS Digital Circuits Families for Low-Power Applications", Workshop Proceedings, pp. 129-132, 1994.