Implementation Of RS Decoder Using High-Speed UHD Architecture
Bhashipaka. Ashok, M. A. Himayath Shamshi
Keywords : Burst error correction, Hard decision decoding,u nified VLSI architecture.
Abstract: Reed-Solomon (RS) codes are widely used as f orward correction codes (FEC) in digital com munication and storage systems.correcting ran random errors of RS codes have been extensiv ely studied in both academia and industry. Ho wever, for burst-error correction, the research is still quite limited due to its ultra high compu tation complexity. In this brief, starting from a recent theoretical work, a low-complexity refo rmulated inversionless burst-error correcting (RiBC) algorithm is developed for practical ap plications.Then, based on the proposed algorit hm, a unified VLSI architecture that is capabl e of correcting burst errors, as well as random errors and erasures, is firstly presented for mu lti-mode decoding requirements. This new arc hitecture is denoted as unified hybrid decoding (UHD)architecture. It will be shown that,being the first RS decoder owning enhanced burst er ror correcting capability, it can achieve signifi cantly improved error correcting capability th an traditional hard-decision decoding (HDD) design. A design of (7, 3) Reed Solomon encod er and Decoder are implemented using VHDL hardware description language (HDL) code, sim ulated and synthesized by XILINX ISE simulator.
General Terms : Burst errors, Reed-Solomon codes,RiBC algorith m and UHD architecture.
. D. V. Sarwate and N. R. Shanbhag, “High-sp eed architectures for “Reed-Solomon decoders,” IEEE Trans. Very Large Scale Integr.(VLSI) syst. , vol. 9, no. 5, pp. 641–655, Oct. 2001.
. T. Zhang and K. K. Parhi, “On the high-speed VLSI implementation of errors-and-erasures corr correcting Reed-Solomon decoders,” in Proc. ACM Great Lake Symp. VLSI (GLVLSI), 2002,PP . 89–93.
. Z. Wang and J. Ma, “High-speed interpolation architecture for soft-decision decoding of Reed-Solomon codes, ” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 9, pp. 937–950, Sep.2006.
. E. Dawson and A. Khodkar, “Burst error corr ecting algorithm for Reed-Solomon codes,” Elect ron. Lett., vol. 31, pp. 848–849, 1995.
. L. Yin, J. Lu, K. B. Letaief, and Y. Wu, “Burst-error-correcting algorithm for Reed Solom on codes,” Electron. Lett., vol. 37, no. 11, pp.695 –697, May 2001.
. Y. Wu, “Novel burst error correcting algorith ms for Reed-Solomon codes,” in Proc. IEEE Allerton Conf. Commun., Control, Comput.,2009, pp. 1047–1052.
. S. Shamshiri and K.-T. Cheng, “Error locali- ty aware linear coding to correct multi-bit upsets in SRAMs,” in Proc. IEEE Int. Test Conf., 2009.
. B.Sklar, “ Digital Communication Fundamen- tal and Application” Prentice Hall, Upper Saddle River, 2001.p.1104.
. S.B.Wicker and V.K. Bhargava, eds “Reed-Solomon codes and their applications” New york: IEEE press 1994.
. Amina, P. Chio, I.A. Sahagun and D. J. Sab- ido IX “ VLSI Implementation of A (255,223) Reed- Solomon Error- Correction Codes ,” Roc. Of Second National ECE Conference.
. Li Li, Bo Yuan “ Unified Architecture for Reed-Solomon decoder combined with burst error correction”, IEEE transaction on VLSI systems,JULY 2012.
. J.H. van Lint, “ Introduction to Coding Theory.Springer, New York 3rd Edition,1999.
. W. Cary Hu_man; Vera Pless, “ Funda- mentals of Error-Correcting Codes” . Cambr- idge University Press; Cambridge, UK 1st Edition, 2010.
. J.L. Massey, “ Shift-register synthesis and BCH decoding," IEEE Trans. Inform. Theory IT-15 (1969).
. K.A.S. Immink, “ Reed- Solomon codes and the compact disc," in Reed-Solomon Codes and Their Applications, eds. S.B. Wicker and V.K. Bhargava. New York: IEEE Press, 1994, pp.41-59