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IJSTR >> Volume 9 - Issue 5, May 2020 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



A Study On Test Pattern Generation Using Arithmetic Approach For Iscas 85 Benchmark Circuits

[Full Text]

 

AUTHOR(S)

J. Poornimasre, R. Harikumar, P. Saravanakumar

 

KEYWORDS

Test pattern Generation, Fault coverage, Test Application Time, Circuit under Test

 

ABSTRACT

Test patterns are needed to test the functionality of integrated circuits. Most of the semiconductor industry depends EDA tool to generate patterns and are applied to the Circuit under Test (CUT) to check the functional verification of the circuit [1]. Those generated test patterns are insufficient in terms of (Test Application Time) TAT and Fault coverage. Important issues in testing is to detect more faults with minimized test patterns, reduce the test power and test application time. Test application time (TAT) is directly proportional to number of test patterns. An arithmetic approach is proposed to modify the test set in order to reduce the total test set. The test patterns of ISCAS 85 benchmark circuits has taken as reference for this work. Fault coverage and TAT are analyzed for each ISCAS’85 benchmark circuits. Experimental results shows that an arithmetic approach reduce the TAT without degrading the fault coverage.

 

REFERENCES

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