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IJSTR >> Volume 8 - Issue 8, August 2019 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



A Study Of Fault Tolerance In High Speed VLSI Circuits

[Full Text]

 

AUTHOR(S)

Somashekhar, Dr.Vikas Maheshwari, Dr.R. P. Singh

 

KEYWORDS

VLSI, Fault Tolerance, Errors, CED, Watchdogs, Processor, Processing Element, Wafer, TMR and DMR.

 

ABSTRACT

The main motive for introducing fault tolerance in VLSI circuits is yield enhancement, by increasing the percentage of fault free chips. In nm technologies, circuits are more and more sensitive to a variety of perturbations. Transient faults can take place in a processor as a result of electrical noise, and alpha particles. These faults are able to cause a program running on the processor to behave inconsistently, if they propagate and change the architectural state of the processor. These faults can occur in memory arrays, sequential elements or in the combinational logic in the processor. Protection against transient faults in combinational logic has not received much attention traditionally because combinational logic has a natural barrier stopping the propagation of the faults. This paper presents fault tolerance in VLSI circuits.

 

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