IJSTR

International Journal of Scientific & Technology Research

Home About Us Scope Editorial Board Blog/Latest News Contact Us
0.2
2019CiteScore
 
10th percentile
Powered by  Scopus
Scopus coverage:
Nov 2018 to May 2020

CALL FOR PAPERS
AUTHORS
DOWNLOADS
CONTACT

IJSTR >> Volume 9 - Issue 8, August 2020 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



A Data Recovery Technique Improves On Hybrid-Mapping For NAND Flash Memory

[Full Text]

 

AUTHOR(S)

Van-Dai Tran and Dong-Joo Park

 

KEYWORDS

NAND Flash memory, Data recovery technique, ECC, Power Loss Recovery, and Spare area.

 

ABSTRACT

Flash memory has been built upon EEPROM (Electronically Erasable Programmable Read-Only Memory). Unlike traditional magnetic disks, Flash memory has disadvantages, like the limitations of life cycle and erase-before-write, which require a resolution well-known namely Flash Translation Layer (FTL) to resolve. Volatile memory today is used to save periodic retrieve requests for mapping-tables in flash memory. These tables can be missed when an unexpected power outage occurs. In order to address this problem, Page-mapping, Block- mapping, and Hybrid-mapping methods have been introduced. However, these methods also have shortcomings, for example, the mapping-information management overhead and the recovery time. In this paper, we introduce a data recovery scheme improves on Hybrid-mapping together with the spare area separate to ECC (Error Code Correction), block information, ASN (Allocation Sequence Number), mapping-information, Flag, and reserved in FTL. The results display that our technique has the less recovery time and mapping-information management overhead than the previous methods.

 

REFERENCES

[1] T.-S. Chung, D.-J. Park, S. Park, D.-H. Lee, S.-W. Lee and H.-J. Song, “A Survey of Flash Translation Layer”, Journal of Systems Architecture, vol. 5-6, no. 55, (2009), pp. 332-343.
[2] T-S. Chung, M. Lee, Y. Ryu, and K. Lee, “PORCE: An efficient power off recovery scheme for flash memory”, Journal of Systems Architecture, vol. 10, no. 54, (2008), pp. 935-943.
[3] S. Jung and YH. Song, “Data loss recovery for power failure in flash memory storage systems”, Journal of Systems Architecture, vol. 1, no. 61, (2015), pp. 12-27.
[4] J.-H. Chung and T.-S. Chung, “HYFLUR: recovery for power-off failure in flash memory storage systems using HYbrid FLUsh recovery”, Information science and applications (ICISA 2016), no. 376, (2016), pp. 501-510.
[5] J.-H. Chung, S. Kim and T.-S. Chung, “C-HYFLUR: Recovery for Power-off Failure in Flash Memory Storage Systems Using Compression Scheme for HYbrid FLUsh Recovery”, International Conference on Mobile and Wireless Technology (ICMWT 2017): Mobile and Wireless Technologies, (2017), pp. 284-294.
[6] J. Ziv and A. Lempel, “A universal algorithm for sequential data compression”, IEEE Transactions on Information Theory 23, vol. 3, no. 23, (1977), pp. 337-343.
[7] S. Jung, S. Lee, H. Jung and YH. Song, “In-page management of error correction code for MLC flash storage systems”, IEEE Trans. Consum. Electron, vol. 2, no. 56, (2010), pp. 339-347.
[8] BW. Nam, GJ. Na, SW. Lee, “A hybrid flash memory ssd scheme for enterprise database applications”, International Asia-Pacific Web Conference (APWEB), IEEE, (2010), pp. 39–44.
[9] S. Im, D. Shin, “Comboftl: Improving performance and lifespan of mlc flash memory using slc flash buffer”, Journal of Systems Architecture 2010, vol. 12, no. 56, (2010), pp. 641–653.
[10] Y. Oh, E. Lee, J. Choi, D. Lee, SH. Noh, “Hybrid solid state drives for improved performance and enhanced lifetime”, Symposium on Mass Storage Systems and Technologies (MSST), (2013), pp. 1–5.
[11] R. Chen, Z. Qin, Y. Wang, D. Liu, Z. Shao, Y. Guan, “On-demand block-level address mapping in large-scale nand flash storage systems”, IEEE Transactions on Computers 2015, vol. 6, no. 64, (2015), pp. 1729–1741.
[12] S. Im, D. Shin, “Storage architecture and software support for slc/mlc combined flash memory”, Proceedings of the 2009 ACM symposium on Applied Computing, (2009), pp. 1664–1669.
[13] R. Micheloni, A. Marelli and R. Ravasio, “Error Correction Codes for Non-Volatile Memories”, Springer-Verlag, (2008).
[14] R. Micheloni, R. Ravasio, A. Marelli, E. Alice, V. Altieri, A. Bovino, L. Crippa, E. Di Martino, L. D'Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone, M. Romano, M. Sangalli, P. Sauro, M. Scotti and S. Won. “A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput”, IEEE International Solid-State Circuits Conference Dig. Tech. Papers, (2006), pp. 142-143.
[15] Avinash Aravindan, “Flash 101: NAND Flash vs NOR Flash”, Available online: https://www.embedded.com /flash-101-nand-flash-vs-nor-flash. (Accessed on September, 2019).
[16] Samsung Electronics, K9LCG08U1A Data sheet online. Available online: http://www.datasheet-pdf.com/ PDF/ K9LCG08U1A-Datasheet-Sam-sung-704175. (Accessed on September, 2019).
[17] Indilinx Jasmine Platform Specification. Available online: http://www.openssd-project.org/wiki/ Jasmine_OpenSSD_Platform. (Accessed on September, 2019).
[18] Samsung Electronics, K4M51323LC Data sheet online. Available online: http://www.datasheet-pdf.com/PDF/K4M51323LC-F-Datasheet-Samsungsemiconductor-659502. (Accessed on September, 2019).
[19] [19] V.-D. Tran, D.-J. Park, A survey of data recovery on flash memory, International Journal of Electrical and Computer Engineering, (2020), 360-376, 10(1).