On Chip Calibration For A 7 Bit Comparator Based Asyncronous Binary Search (CABS) A/D Converter
Vikash Kumar Singh, Kumari Archana
Index Terms: 2-step 8-bit ADC Architecture, Calibration of 7-bit CABS ADC, 7-bit CABS stage
Abstract: An on-chip calibration technique has been proposed for a 7-bit Comparator Based Asynchronous Binary Search (CABS) A/D Converter. The proposed design is veri-fied using an 8-bit, 3.3V, 10 MS/s Asynchronous SAR A/D Converter by integrating the calibration scheme into the A/D Converter. The 8-bit Asynchronous SAR A/D Converter consists of a track-and-hold followed by a two-step conversion process. The two-step architecture consists of a 1-bit course and a 7-bit fine converter. The 1-bit coarse converter is implemented using the SAR-CC principle and the 7-bit fine converter is implemented using the CABS principle. The 7-bit CABS sub-A/D converter consists of 127 comparators with differ-ent threshold voltages. All these 127 comparators with different threshold voltages are calibrated using a calibration technique in which the thresholds are adjusted to the desired value by tuning the total current flowing through the differential pair in the comparator circuit. The calibration technique and the A/D converter have been designed in 0.18 mm CMOS technology with a supply voltage of 3.3 V. The simulation results showed an ENOB of 6.7 for SNDR of 42.09 dB at Nyquist frequency.
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