IJSTR

International Journal of Scientific & Technology Research

IJSTR@Facebook IJSTR@Twitter IJSTR@Linkedin
Home About Us Scope Editorial Board Blog/Latest News Contact Us
CALL FOR PAPERS
AUTHORS
DOWNLOADS
CONTACT
QR CODE
IJSTR-QR Code

IJSTR >> Volume 2- Issue 11, November 2013 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



On Chip Calibration For A 7 Bit Comparator Based Asyncronous Binary Search (CABS) A/D Converter

[Full Text]

 

AUTHOR(S)

Vikash Kumar Singh, Kumari Archana

 

KEYWORDS

Index Terms: 2-step 8-bit ADC Architecture, Calibration of 7-bit CABS ADC, 7-bit CABS stage

 

ABSTRACT

Abstract: An on-chip calibration technique has been proposed for a 7-bit Comparator Based Asynchronous Binary Search (CABS) A/D Converter. The proposed design is veri-fied using an 8-bit, 3.3V, 10 MS/s Asynchronous SAR A/D Converter by integrating the calibration scheme into the A/D Converter. The 8-bit Asynchronous SAR A/D Converter consists of a track-and-hold followed by a two-step conversion process. The two-step architecture consists of a 1-bit course and a 7-bit fine converter. The 1-bit coarse converter is implemented using the SAR-CC principle and the 7-bit fine converter is implemented using the CABS principle. The 7-bit CABS sub-A/D converter consists of 127 comparators with differ-ent threshold voltages. All these 127 comparators with different threshold voltages are calibrated using a calibration technique in which the thresholds are adjusted to the desired value by tuning the total current flowing through the differential pair in the comparator circuit. The calibration technique and the A/D converter have been designed in 0.18 mm CMOS technology with a supply voltage of 3.3 V. The simulation results showed an ENOB of 6.7 for SNDR of 42.09 dB at Nyquist frequency.

 

REFERENCES

[1] M.Waltari and K. Halonen, Circuit techniques for low-voltage and high-speed A/D converters. Springer, 2002, vol. 709.

[2] G. Van der Plas and B. Verbruggen, A 150MS/s 133mW 7b ADC in 90nm digital CMOS Using a Comparator-Based Asynchronous Binary-Search sub-ADC, in Solid-State Circuits Conference, 2008. ISSCC 2008. Digest of Technical Papers. IEEE International. IEEE, 2008, pp. 26312640.

[3] M. Mano and M. Ciletti, Digital design, 1984.

[4] G. Yeap, Practical low power digital VLSI design. Springer, 1998.

[5] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital integrated circuits. Prentice-Hall, 1996.

[6] R. Baker, CMOS Mixed Signal Circuit Design. John Wiley & Sons, 2008.