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IJSTR >> Volume 2- Issue 11, November 2013 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Serial Front Panel Data Port (SFPDP) Protocol Implementation In Xilinx Fpgas

[Full Text]

 

AUTHOR(S)

M. Vanaja, P. Prasanth Babu.

 

KEYWORDS

Index Terms: FPDP (Front Panel Data Port), SFPDP (Serial Front Panel Data Port), XAUI (Extended Attachment Unit Interface), FPGA (Field Programmable Gate Array), SOF (Start of Frame), SEOF (Status End Of Frame), FEOF (Frame End Of Frame), MEOF (Mark End Of Frame).

 

ABSTRACT

Abstract: The Serial Front Panel Data Port (SFPDP) protocol for high speed data transfer presents in this paper. High-speed data transfer finds application in most modern day communication systems. This design has been mainly done for data transfer in radar systems but can be programmed and used for variety of applications involving high-speed data transfer. The design follows a systematic approach with design of SFPDP protocol and implementation on FPGA and explains all these stages of design in detail. The design can be programmed to work at different speeds as required by different systems and thus can be used in variety of systems involving high-speed data transfers. The efficient use of customized IP cores and resources of FPGA delivers high level of performance and area efficiency.

 

REFERENCES

[1] Volnei A. Pedroni, ‘Circuit Design with VHDL’, MIT Press, England. [2] Charless H. Roth, Jr (2005) ‘Digital Systems Design Using VHDL’, 3rd

[2] Edition, Thomson Asia private limited, Singapore.


[3] Bhaskar .J (2004) ‘A VHDL Primer’, 3rd edition, Pearson Education private limited, Singapore.

[4] Merrill I. Skolnik (2001) ‘Introduction to RADAR systems’, 3rd edition.


[5] Tata McGraw-Hill publishing company limited. Singapore. [5] Virtex-5 FPGA XAUI User Guide.

[6] ISE Design Suite 11.1 Release Notes and Installation Guide.


[7] SFPDP Draft standard vita 17.1-200x.

[8] Xilinx IP Cores User Guide.