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IJSTR >> Volume 8 - Issue 11, November 2019 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



An Efficient Directional Routing Algorithm For Network On Chip

[Full Text]

 

AUTHOR(S)

Venkateswara Rao Musala, Venkata Rama Krishna Tottempudi

 

KEYWORDS

Avg. Latency, Directional Routing Algorithm (DRA), Network-on-Chip (NoC), Resistance and Capacitance (RC), System on chip (SoC), Throughput .

 

ABSTRACT

Bus structures are commonly used in System on Chip (SoC) which needs a lot of wiring that causes an increase in Resistance and Capacitance (RC) of the framework in SoC. To avoid this an interconnection network called Network on Chip (NoC) is introduced for better communication in terms of latency and throughput among the processing cores in the vicinity of the selected network. It plays a major role to dress the issues in SoC. An on-chip routing resource is used to send the data packet based on routing decisions done in the router, which improves performance of interconnection fabric in terms of latency and throughput over resolute wiring and buses. Present routing algorithms in NoC experience a problem of channel load imbalance, which causes congestion in the routed path and effects the latency and throughput of the routed packet. This work proposes an adaptive routing resource fabric (Directional Routing Algorithm (DRA)) to avoid the congestive paths by identifying the unloaded path with the help of timeout piggybacking and load shedding, the DRA bypasses the congested path on the channel, based on direction specific traffic patterns. The proposed algorithm does better than Normal XY routing by 18% and 31% in terms of Avg.latency and throughput

 

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