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IJSTR >> Volume 9 - Issue 1, January 2020 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Comparison Analysis Of N-Channel And P-Channel SOI / Bulk Finfets

[Full Text]

 

AUTHOR(S)

V Vijayalakshmi , Dr. B. Mohan Kumar Naik

 

KEYWORDS

nFinFET, pFinFET, SOI FinFET, Bulk FinFET, Drain Current.

 

ABSTRACT

In this research paper, a 3 dimensional device simulation of 20 nm n-channel and p-channel SOI FinFET and Bulk FinFET have been studied. The electrical parameters such as electrostatic potential, electric field, current density, transfer characteristics, output characteristics, drive current, OFF state current and transconductance are investigated based on the various bias voltages. The transfer characteristics of SOI FinFETs are compared with that of bulk FinFETs. Based on the comparison analysis SOI FinFETs are more dominant over bulk FinFETs because of large ION/IOFF ratio in wide circuit applications and semiconductor memories.

 

REFERENCES

[1] Sung-Jae Chang, Maryline Bawedin, Yufeng Guo, Fanyu Liu, Kerem Akarvardar, Jong-Hyun Lee,Jung-Hee Lee, Irina Ionica, Sorin Cristoloveanu, “Enhanced coupling effects in vertical double-gate FinFETs”, Solid-State Electronics 97 (2014) 88–98.
[2] Reena Sonkusare, Omkar Joshi, S.S. Rathod, “SOI FinFET based instrumentation amplifier for biomedical applications”, Microelectronics Journal 91 (2019) 1–10.
[3] Qi Chenga, Kazy Shariara, Sourabh Khandelwalb, Yuping Zenga, “DC and RF performances of InAs FinFET and GAA MOSFET on insulator”, Solid State Electronics 158 (2019) 11–15.
[4] S. Chander , S. Baishya, S.K. Sinha, S. Kumar, P.K. Singh, K. Baral, M.R. Tripathy, A.K. Singh, S. Jit, “Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs”,Superlattices and Microstructures 131 (2019) 30–39.
[5] Aayush Gupta, Ruchir Mathur, M. Nizamuddin, “Design, simulation and comparative analysis of a novel FinFET based astable multivibrator”, Int. J. Electron. Commun. (AEÜ) 100 (2019) 163–171.
[6] Lucas Prilenski , P.R. Mukund, “A sub 1-volt subthreshold bandgap reference at the 14 nm FinFET node”, Microelectronics Journal 79 (2018) 17–23.
[7] N. P. Maity, Reshmi Maity, Srimanta Baishya, “An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET”, Journal of Computational Electronics (2019) 18:65–75.
[8] A.L. Zimpeck , C. Meinhardt, R.A.L. Reis, “Impact of PVT variability on 20 nm FinFET standard cells”, Microelectronics Reliability 55 (2015) 1379–1383.
[9] Wen-Tsung Huang and Yiming Li, “Electrical characteristic fluctuation of 16-nm-gate
trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants”, Nanoscale Research Letters (2015) 10:116.
[10] Nebojsa D. Jankovic, Chadwin D. Young , “Experimental Evaluation of Circuit-Based Modeling of the NBTI Effects in Double-Gate FinFETs”, Microelectronics Reliability 59 (2016) 26–29.
[11] Abhijeet Walke , Garrett Schlenvogt , Santosh Kurinec , “Design strategies for ultra-low power 10 nm FinFETs”, Solid-State Electronics 136 (2017) 75–80.
[12] Mohamed Mounir Mahmouda, Norhayati Soinb , “A comparative study of lifetime reliability of planar MOSFET and FinFET due to BTI for the 16 nm CMOS technology node based on reaction-diffusion model”, Microelectronics reliability 97 , 2019,pp 53-65.
[13] Yu-Fan Chiang, Wei-Yu Chien, Yue-Der Chih, Jonathan Chang, Chrong Jung Lin, Ya-Chin King, “FinFET CMOS logic gates with non-volatile states for reconfigurable computing systems”, Integration, the VLSI Journal 65 (2019) 97–103.
[14] ATLAS: Device simulation software. Silvaco Int, Santa Clara (2012).