IJSTR

International Journal of Scientific & Technology Research

Home About Us Scope Editorial Board Blog/Latest News Contact Us
0.2
2019CiteScore
 
10th percentile
Powered by  Scopus
Scopus coverage:
Nov 2018 to May 2020

CALL FOR PAPERS
AUTHORS
DOWNLOADS
CONTACT

IJSTR >> Volume 9 - Issue 3, March 2020 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Compact Qca Based Serial-Parallel Multiplier For Signal Processing Applications

[Full Text]

 

AUTHOR(S)

Premananda B.S., Bhargav U.K., Kaza Sai Vineeth

 

KEYWORDS

QCA, QCADesigner-E, Serial adder, Serial-parallel multiplier, Parallel multiplier.

 

ABSTRACT

Quantum-dot Cellular Automata (QCA) is a promising nanoscale technology with great prospect to provide compact circuits with low energy consumption when compared to CMOS technology. The increasing demand for efficient signal processors necessitates the design of adders and multipliers which occupy less area and consume less power. Serial adders are area efficient architectures that can compute n-bit addition with a single adder but takes more time when compared to n-bit parallel adders. Serial-parallel multipliers have simple, regular and scalable structures in contrast to multipliers that implement more complex multiplication algorithms. This paper proposes two novel energy and area efficient 4-bit QCA based serial-parallel multiplier circuits. Initially a QCA based serial adder is designed and then a 2-bit serial-parallel multiplier is realized. This multiplier is scaled up to form a 4-bit serial-parallel multiplier. A Baugh-Wooley (parallel) multiplier is constructed as a case study to illustrate differences between coplanar and multilayer crossovers in QCA. The design and simulation of the QCA circuits are performed using QCADesigner-E. Circuits are evaluated based on cell count, area and energy dissipation. It can be inferred from the simulation results that the proposed 4-bit serial-parallel multipliers have reduced cell count, area and energy dissipation.

 

REFERENCES

[1] F.S. Torres, R. Wille, P. Niemann, and R. Drechsler (2018). An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular Automata. IEEE Transactions on CAD of Integrated Circuits and Systems, 1-11.
[2] K. Walus, T.J. Dysart, G. A. Jullien, and R. A. Budiman (2004). QCA Designer: A Rapid Design and Simulation Tool for Quantum-Dot Cellular Automata IEEE Transactions on Nanotechnology, 3: 26-31.
[3] C. S. Lent, P. D. Tougaw, W. Porod, and G. H. Bernstein (1993). Quantum Cellular Automata. Nanotechnology, 4(1): 49-58.
[4] Premananda B. S., Bhargav U. K., and Kaza Sai Vineeth (2018). Design and Analysis of Compact QCA Based 4-Bit Serial-Parallel Multiplier. Proceedings of the 2nd IEEE International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques, 1014 to 1018. (in press).
[5] K. Kim, K. Wu, and R. Karri (2007) The Robust WCA Adder Designs using Composable QCA Building Blocks. IEEE Transactions on CAD of Integrated Circuits and Systems. 26 (1), 176-183.
[6] Namita and T. N. Sasamal (2017) Design of 4-Bit Serial-Parallel Multiplier in Quantum-Dot Cellular Automata. Proceedings of the IEEE International Conference on Signal Processing, Computing and Control. 1-4.
[7] W. Liu, L. Lu, M. O'Neill, and E. E. Swartzlander, (2011). Design Rules for Quantum-Dot Cellular Automata. IEEE International Symposium on Circuits and Systems. 2361-2364.
[8] D. Abedi, and G. Jaberipur, (2015). Coplanar QCA Serial Adder and Multiplier via Clock-Zone based Crossover. Proceedings of the IEEE CSI International Symposium on Computer Architecture and Digital Systems. 1-4.
[9] I. Hänninen and J. Takala. (2010). Binary Adders on Quantum-Dot Cellular Automata. Journal of Signal Processing Systems. 58(1): 87-103.
[10] I.E. Arani and A. Rezai, (2018). Novel Circuit Design of Serial-parallel Multiplier in Quantum-Dot Cellular Automata Technology. Journal of Computational Electronics. 1-9.
[11] Kalogeiton et al., (2017). Programmable Crossbar Quantum-Dot Cellular Automata Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 36(8): 1367-1380.
[12] Premananda B. S., and Ganavi M. G. (2019). Performance Analysis of Low Power 8-Tap FIR Filter using PFAL. International Journal of Innovative Technology and Exploring Engineering. 8(8): 365-374.
[13] K. Navi, R. Farazkish, S. Sayedsalehi, and M. R. Azghadi (2010). A New Quantum-Dot Cellular Automata Full-Adder. Journal of Microelectronics. 41(12): 820-826.
[14] Vinay B. Biradar, Vishwas P.G., Chetan C.S., and Premananda B. S., (2017). Design and Performance Analysis of Modified Unsigned Braun and Signed Baugh Wooley Multiplier. Proceedings of the 2nd IEEE International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques., pp. 1-5.
[15] H. Cho, and E.E. Swartzlander (2009). Adder and Multiplier Design in Quantum-Dot Cellular Automata. IEEE Transactions on Computers. 58(6): 721-727.