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IJSTR >> Volume 5 - Issue 7, July 2016 Edition



International Journal of Scientific & Technology Research  
International Journal of Scientific & Technology Research

Website: http://www.ijstr.org

ISSN 2277-8616



Redundant Radix-4 Representation With High Speed Arithmetic Coprocessor Using Carry Save And Redundant Signed Digit Technique

[Full Text]

 

AUTHOR(S)

Ashish Manoharrao Ingale

 

KEYWORDS

Redundant Radix-4 (RR-4), Carry Save (CS), Redundant Signed Digit (RSD), Carry Propagate Adder (CPA).

 

ABSTRACT

Division is the “inverse” of multiplication so basic division consist of a sequence of subtraction, which are just additions of the negations of the subtrahends; Therefore, CS addition can be used in the arithmetic for division as well. Division is, however more complicated than multiplication, in that subtrahend (multiple of divisor) chosen at any steps depends on the magnitude result of the preceding subtraction and that magnitude is not readily available with CS representation. Assuming two’s complement representation, subtraction with carry save representation is carried out in usual manner of the farming the one’s complement of the subtrahend and then adding that with a 1 also added into the least significant bit position subtraction is performed by adding the negation of the subtrahend, which two’s complement representation consist of the one’s complement addition of 1 in the least significant bit position.

 

REFERENCES

[1] G. Jaberipur, B. Parhami, M. Ghodsi, Weighted bit-set encodings for redundant digit sets: theory and applications, in: Proceedings of 36th Asilomar Conference on Signals, Systems and Computers, 2002, pp. 1629–1633.

[2] G. Jaberipur, B. Parhami, M. Ghodsi, Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems, IEEE Trans. Circuits Syst. I 52 (7) (2005) 1348–1357.

[3] G. Jaberipur, B. Parhami, Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic, IET Circuits Devices Syst. 1 (1) (2007) 102–110.

[4] G. Jaberipur, B. Parhami, Constant-time addition with hybrid-redundant numbers: theory and implementations, Integration VLSI J. 41 (1) (2008) 49–64.

[5] R.D. Kenney, M.J. Schulte, M.A. Erle, A high-frequency decimal multiplier, in: IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD), 2004, pp. 26–29

[6] R.D. Kenney, M.J. Schulte, High-speed multioperand decimal adders, IEEE Trans. Comput. 54 (8) (2005) 953–963.

[7] T. Lang, A. Nannarelli, A radix-10 combinational multiplier, in: Proceedings of Asilomar Conference on Signals, Systems, and Computers, 2006, pp. 313–317.

[8] T. Lang, A. Nannarelli, A radix-10 digit-recurrence division unit: algorithm and architecture, IEEE Trans. Comput. 56 (6) (2007) 727–739.

[9] G. Metze, J.E. Robertson, Elimination of Carry propagation in digital computers, in: Proceedings of International Conference on Information Processing, Paris, 1959, pp. 389–396.

[10] H. Nikmehr, B.J. Phillips, C.C. Lim, A decimal carry-free adder, in: Proceedings of SPIE Conference on Smart Materials, Nano-, Micro-Smart Systems, 2004, pp. 786–797.

[11] H. Nikmehr, B. Phillips, C.C. Lim, Fast decimal floating-point division, IEEE Trans. Very Large Scale Integration (VLSI) Syst. 14 (9) (2006) 951–961.

[12] B. Parhami, Generalized signed-digit number systems: a unifying framework for redundant number representations, IEEE Trans. Comput. 39 (1) (1990) 89–98.

[13] R.K. Richards, Arithmetic Operations in Digital Computers, Van Nostrand Comp., Inc., 1955.

[14] M. Schmookler, A. Weinberger, High speed decimal addition, IEEE Trans. Comput. C-20 (8) (1971) 862–866.

[15] S. Shankland, IBM’s POWER6 gets help with math, multimedia, ZDNet News (2006).

[16] B. Shirazi, D.Y. Yun, C.N. Zhang, RBCD: redundant binary coded decimal adder, in: IEE Proceedings on Computer & Digital Techniques (CDT), vol. 36, no. 2, 1989.

[17] I.E. Sutherland, R.F. Sproull, D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, Los Altos, CA, ISBN 1558605576, 1999.

[18] A. Svoboda, Decimal adder with signed digit arithmetic, IEEE Trans. Comput. C-18 (3) (1969) 212–215.


[19] A. Vazquez, E. Antelo, P. Montuschi, A new family of high-performance parallel decimal multipliers, in: Proceedings of the 18th IEEE Symposium on Computer Arithmetic, 2007, pp. 195–204.

[20] L. Wang, M.J. Schulte, A decimal floating-point divider using Newton– Raphson iteration, J. VLSI Signal Process. Syst. 14 (1) (2007) 3–18.

[21] C.K. Yuen, A new representation for decimal numbers, IEEE Trans. Comput.C-26 (12) (1977) 1286–1288.