IJSTR >> Volume 9 - Issue 10, October 2020 Edition

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AUTHOR(S)

Mahesha Y, Priya Seema Miranda, Jayalakshmi K P, Keerthana Bhandarkar, Aniceta Priya Dsouza

KEYWORDS

Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry Increment Adder (CIA), Carry Select Adder (CSA), Kogge Stone Adder (KSA), Low Power, Wearable devices.

ABSTRACT

An adder is a device used to perform arithmetical functions in electronic calculators and digital instruments and has a wide range of applications. The major factor involved in driving all these instruments is Power. As the power consumption of a device increases, the life span of device reduces. In order to maintain longer life of the device, it is necessary that the power consumption is less. A device is considered efficient when it consumes low power and has high speed. The purpose of this study is to investigate the power and delay product of the adders. The adders that have been compared are all of 12 bit and have been synthesized and simulated using the Cadence software. The outcomes of different properties obtained from the synthesis reports and simulation of the circuit helps in finding out the adder with minimum power and delay product. The adders that have been compared in this paper are Ripple Carry Adder (RCA), Carry Look Ahead Adder (CLA), Carry Increment Adder (CIA), Carry Select Adder (CSA) and Kogge Stone Adder (KSA).

REFERENCES

[1] Vinny Wilson, “Analysis and Performance Evaluation of 1-bit Full Adder Using Different Topologies”, International Journal of Engineering Research and General Science, Volume5, Issue 1, Feb. 2017
[2] Kunjan D. Shinde, Jayashree C. Nidagundi, “Design of fast and efficient 1-bit full adder and its performance analysis”, 2014 International Conference on Control, Instrumentation ,Communication and Computational Technologies (ICCICCT), Volu me 3, No. 3, July, 2014
[3] K Mariya Priyadarshini, R. S. Ernest Ravindran, P. Ratna Bhaskar, “A Detailed Scrutiny and Reasoning on VLSI Binary Adder Circuits and Architectures”, International Journal of Innovative Technology and Exploring Engineering (IJITEE), Volume 8, Issue 7, May,2019
[4] Ashish Bagwari, Isha Katna, “Low Power Ripple Carry Adder Using Hybrid 1-Bit Full Adder Circuit”, 2019 11th International Conference on Computational Intelligence and Communication Networks (CICN), Nov 2019
[5] Patel Chandrahash, C. S. Veena, “Ripple Carry Adder Design Using Universal Logic Gates”, Research Journal of Engineering Sciences, Volume 3, No. 11, Nov 2014
[6] O. L. MacSorley,” High-speed arithmetic in binary computers,” Proc. IRE, vol. 49, Jan.1961, pp. 67-91.
[7] M. Hasan, P. Biswas, M. S. Alam, H. U. Zaman, M. Hossain and S. Islam, ”High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder,” 201910th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Kanpur, India, 2019, pp. 1-5, doi: 10.1109/ICCCNT45670.2019.8944524.
[8] S Devi, Aribam & Kumar, Manoj & Laishram, Romesh. (2016). Design and Implementation of an Improved Carry Increment Adder. International Journal of VLSI Design &Communication Systems. 7. 21-27. 10.5121/vlsic.2016.7103
[9] Natarajan, P. and Ghosh, Samit and Karthik, Rajesh, ”Low power high performance carry select adder”,601-603,(2017), doi:10.1109/ICECA.2017.8212736
[10] U. Penchalaiah and S. K. VG, ”Design of High-Speed and Energy- Efficient Parallel Prefix Kogge Stone Adder,” 2018 IEEE International Conference on System, Computation, Automation and Networking (ICSCA), Pondicherry, 2018, pp. 1-7, doi: 10.1109/IC-SCAN.2018.8541143.